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19-0435; Rev 0; 9/95
KIT ATION EVALU ILABLE AVA
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
____________________________Features
o 12-Bit Resolution, 1/2LSB Linearity o Single +5V Supply Operation o Software-Selectable Input Ranges: 10V, 5V, 0V to +10V, 0V to +5V (MAX196) VREF, VREF/2, 0V to +VREF, 0V to +VREF/2 (MAX198) o Internal 4.096V or External Reference o Fault-Protected Input Multiplexer o 6 Analog Input Channels o 6s Conversion Time, 100ksps Sampling Rate o Internal or External Acquisition Control o Two Power-Down Modes o Internal or External Clock
_______________General Description
The MAX196/MAX198 multirange, 12-bit data-acquisition systems (DAS) require only a single +5V supply for operation, yet convert analog signals at their inputs up to 10V (MAX196) and 4V (MAX198). These systems provide six analog input channels that are independently software programmable for a variety of ranges: 10V, 5V, 0V to +10V, and 0V to +5V for the MAX196; VREF, VREF/2, 0V to +VREF, and 0V to +VREF/2 for the MAX198. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 12V, 15V, and 4mA to 20mA powered sensors to a single +5V system. In addition, these converters are fault protected to 16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps throughput rate, software-selectable internal/external clock, internal/external acquisition control, 12-bit parallel interface, and internal 4.096V or external reference. Two programmable power-down modes (STBYPD, FULLPD) provide low-current shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays. The MAX196/MAX198 employ a standard microprocessor (P) interface. A three-state data I/O port is configured to operate with 16-bit data buses, and dataaccess and bus-release timing specifications are compatible with most popular Ps. All logic inputs and outputs are TTL/CMOS compatible. These devices are available in 28-pin DIP, wide SO, SSOP (55% smaller in area than wide SO), and ceramic SB packages. For 8+4 bus interface, see the MAX197 and the MAX199 data sheets. An evaluation kit will be available after December 1995 (MAX196EVKIT-DIP).
MAX196/MAX198
______________Ordering Information
PART MAX196ACNI MAX196BCNI MAX196ACWI MAX196BCWI MAX196ACAI MAX196BCAI TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP
Ordering Information continued at end of data sheet.
__________________Pin Configuration
TOP VIEW
CLK 1 CS 2 D11 3 D10 4 28 DGND 27 V DD 26 WR 25 RD
________________________Applications
Industrial-Control Systems Robotics Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications
D9 5 D8 6 D7 7 D6 8 D5 9 D4 10 D3 11 D2 12 D1 13 D0 14
MAX196 MAX198
24 INT 23 REF 22 REFADJ 21 CH5 20 CH4 19 CH3 18 CH2 17 CH1 16 CH0 15 AGND
Functional Diagram appears at end of data sheet.
DIP/SO/SSOP/Ceramic SB 1
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-722-8266 for free samples or literature.
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +7V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND..............................................-0.3V to (VDD + 0.3V) REFADJ to AGND.......................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) CH0-CH5 to AGND ..........................................................16.5V Continuous Power Dissipation (TA = +70C) Narrow Plastic DIP (derate 14.29mW/C above +70C)....1143mW Wide SO (derate 12.50mW/C above +70C)..............1000mW SSOP (derate 9.52mW/C above +70C) ......................762mW Narrow Ceramic SB (derate 20.00mW/C above +70C)..1600mW Operating Temperature Ranges MAX196_C_ I/MAX198_C_ I .................................0C to +70C MAX196_E_ I/MAX198_E_ I ...............................-40C to +85C MAX196_MYI/MAX198_MYI.............................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity INL DNL Unipolar Offset Error Bipolar Channel-to-Channel Offset Error Matching Unipolar Bipolar Unipolar Gain Error (Note 2) Bipolar Gain Temperature Coefficient (Note 2) Unipolar Bipolar MAX196A/MAX198A MAX196B/MAX198B Up to the 5th harmonic 80 50kHz, VIN = 5V (MAX196) or 4V (MAX198) (Note 3) External CLK mode/external acquisition control External CLK mode/external acquisition control Aperture Jitter Internal CLK mode/internal acquisition control (Note 4) -86 15 <50 10 70 69 -85 -78 MAX196A/MAX198A MAX196B/MAX198B MAX196A/MAX198A MAX196B/MAX198B 3 5 MAX196A/MAX198A MAX196B/MAX198B MAX196A/MAX198A MAX196B/MAX198B 0.1 0.5 7 10 7 10 ppm/C LSB MAX196A/MAX198A MAX196B/MAX198B 12 1/2 1 1 3 5 5 10 LSB LSB Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 10Vp-p (MAX196) or 4.096Vp-p (MAX198), fSAMPLE = 100ksps) Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay SINAD THD SFDR dB dB dB dB ns ps ns
2
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG INPUT Track/Hold Acquisition Time fCLK = 2.0MHz 10V or VREF range Small-Signal Bandwidth -3dB rolloff 5V or VREF/2 range 0V to 10V or 0V to VREF range 0V to 5V or 0V to VREF/2 range MAX196 Unipolar MAX198 Input Voltage Range (see Table 3) VIN MAX196 Bipolar MAX198 MAX196 MAX198 Input Current IIN Bipolar MAX198 Input Resistance Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Output Tempco (Contact Maxim Applications for guaranteed temperature drift specifications) Output Short-Circuit Current Load Regulation Capacitive Bypass at REF REFADJ Output Voltage REFADJ Adjustment Range Buffer Voltage Gain With recommended circuit (Figure 1) VREF TC VREF TA = +25C MAX196_C/MAX198_C MAX196_E/MAX198_E MAX196_M/MAX198_M 0mA to 0.5mA output current (Note 6) 4.7 2.465 2.500 1.5 1.6384 2.535 4.076 4.096 15 30 40 30 10 mA mV F V % V/V ppm/C 4.116 V VIN IIN Unipolar Bipolar (Note 5) MAX196 10V range 5V range VREF range VREF/2 range -1200 -600 -1200 -600 21 16 40 0V to 10V range 0V to 5V range 0.1 0 0 0 0 -10 -5 -VREF -VREF/2 5 2.5 2.5 1.25 10 5 VREF VREF/2 10 5 VREF VREF/2 720 360 10 720 360 10 10 k pF A V MHz 3 s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX196/MAX198
Unipolar
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Voltage Range Input Current VREF = 4.18V Normal, or STANDBY power-down mode FULL power-down mode 10 5 VDD - 50mV SYMBOL CONDITIONS MIN 2.4 TYP MAX 4.18 400 1 k M V UNITS V A
REFERENCE INPUT (buffer disabled, reference input applied to REF pin)
Input Resistance REFADJ Threshold for Buffer Disable POWER REQUIREMENTS Supply Voltage VDD
Normal, or STANDBY power-down mode FULL power-down mode
4.75 Normal mode, bipolar ranges Normal mode, unipolar ranges STANDBY power-down mode FULL power-down mode (Note 7) External reference = 4.096V Internal reference CCLK = 100pF External CLK Internal CLK 1.25 0.1 Internal acquisition 3.0 3.0 3.0 5 6.0 6.0 62 200 CREF = 4.7F CREF = 33F 2.4 8 60 7.7 6 700 60 0.1 1/2 1.56
5.25 18 10 850 120 1/2
V mA A LSB
Supply Current
IDD
Power-Supply Rejection Ratio (Note 8) TIMING Internal Clock Frequency External Clock Frequency Range
PSRR
fCLK fCLK tACQI
2.00 2.0 5.0
MHz MHz
Acquisition Time tACQE Conversion Time Throughput Rate Bandgap Reference Start-Up Time Reference Buffer Settling tCONV
External acquisition (Note 9) After FULLPD or STBYPD External CLK Internal CLK, CCLK = 100pF External CLK Internal CLK, CCLK = 100pF Power-up (Note 10) To 0.1mV REF bypass capacitor fully discharged
s
10.0 100
s ksps s ms
DIGITAL INPUTS (D7-D0, CLK, RD, WR, CS) (Note 11) Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance VINH VINL IIN CIN VIN = 0V or VDD (Note 5) V 0.8 10 15 V A pF
4
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Output Low Voltage Output High Voltage Three-State Output Capacitance SYMBOL VOL VOH COUT CONDITIONS VDD = 4.75V, ISINK = 1.6mA VDD = 4.75V, ISOURCE = 1mA (Note 5) VDD - 1 15 MIN TYP MAX 0.4 UNITS V V pF DIGITAL OUTPUTS (D11-D0, INT)
MAX196/MAX198
TIMING CHARACTERISTICS
(VDD = 5V 5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER CS Pulse Width WR Pulse Width CS to WR Setup Time CS to WR Hold Time CS to RD Setup Time CS to RD Hold Time CLK to WR Setup Time CLK to WR Hold Time Data Valid to WR Setup Data Valid to WR Hold RD Low to Output Data Valid RD High to Output Disable RD Low to INT High Delay Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: SYMBOL tCS tWR tCSWS tCSWH tCSRS tCSRH tCWS tCWH tDS tDH tDO tTR tINT1 Figure 2, CL = 100pF (Note 12) (Note 13) 60 0 120 70 120 CONDITIONS MIN 80 80 0 0 0 0 100 50 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the 10V (MAX196) and 4.096V (MAX198) input ranges. External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground "on" channel; sine wave applied to all "off" channels. Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Guaranteed by design. Not tested. Use static loads only. Tested using internal reference. PSRR measured at full-scale. External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD = high control byte. Not subject to production testing. Provided for design guidance only. All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V. tDO is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. tTR is defined as the time required for the data lines to change by 0.5V.
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX196/8-1
FFT PLOT
MAX196/8-2
EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY
fSAMPLE = 100kHz EFFECTIVE NUMBER OF BITS 11.5
MAX196/8-3
0.250 INTEGRAL NONLINEARITY (LSB) 0.200 0.150
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 fTONE = 10kHz fSAMPLE = 100kHz
12.0
0.100 0.050 0 -0.050 -0.100 -0.150 0 1000 2000 3000 4000 DIGITAL CODE
11.0
10.5
10.0 0 25 FREQUENCY (kHz) 50 1 10 INPUT FREQUENCY (kHz) 100
REFERENCE OUTPUT VOLTAGE (VREF) vs. TEMPERATURE
MAX196/8-4
POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE
VDD = 5V 0.25V 0.2 PSRR (LSB) 0 100Hz -0.2 120Hz
MAX196/8-5 MAX196/8-7
4.100
0.4
4.095 VREF (V)
4.090 AV = 1.6384 +2.5V INTERNAL REFERENCE REFADJ
4.085
REF
-0.4
4.080 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
-0.6 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB)
MAX196/8-6
CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE
0.33 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) 0.32 0.31 0.30 0.29 0.28 0.27 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
0.20
0.18
0.16
0.14
0.12
0.10 -70 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
6
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
______________________________________________________________Pin Description
PIN 1 2 3-14 15 16-21 22 NAME CLK CS D11-D0 AGND CH0-CH5 REFADJ FUNCTION Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode, place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with CCLK = 100pF. Chip Select, active low Three-State Digital I/O, D11 = MSB Analog Ground Analog Input Channels Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect to VDD when using an external reference at the REF pin. Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. INT goes low when conversion is complete and output data is ready. If CS is low, a falling edge on RD will enable a read operation on the data bus. In the internal acquisition mode, when CS is low, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR starts an acquisition, and a second rising edge on WR ends acquisition and starts a conversion cycle. +5V Supply. Bypass with 0.1F capacitor to AGND. Digital Ground
MAX196/MAX198
23 24 25 26 27 28
REF INT RD WR VDD DGND
+5V 510k 100k 0.01F 24k REFADJ
_______________Detailed Description
Converter Operation
The MAX196/MAX198 multirange, fault-tolerant ADCs use successive approximation and internal input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. The 12-bit parallel-output format provides easy interface to microprocessors (Ps). Figure 3 shows the MAX196/MAX198 in the simplest operational configuration.
MAX196 MAX198
Figure 1. Reference-Adjust Circuit
Analog-Input Track/Hold
+5V 3k
DOUT 3k CLOAD DOUT CLOAD
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 2. Load Circuits for Enable Time
In the internal acquisition control mode (control bit D5 set to 0), the T/H enters its tracking mode on WR's rising edge, and enters its hold mode when the internally timed (6 clock cycles) acquisition interval ends. In bipolar mode and unipolar mode (MAX196 only), a lowimpedance input source, which settles in less than 1.5s, is required to maintain conversion accuracy at the maximum conversion rate. When the MAX198 is configured for unipolar mode, the input does not need to be driven from a low-impedance source. The acquisition time (tAZ) is a function of the source output resistance (RS), the channel input resistance (RIN), and the T/H capacitance.
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
Acquisition time is calculated as follows: For 0V to VREF: tAZ = 9 x (RS + RIN) x 16pF For 0V to VREF/2: tAZ = 9 x (RS + RIN) x 32pF where RIN = 7k and tAZ is never less than 2s (0V to VREF range) or 3s (0V to VREF/2 range). In the external acquisition control mode (D5 = 1), the T/H enters its tracking mode on the first WR rising edge and enters its hold mode when it detects the second WR rising edge with D5 = 0 (see External Acquisition section).
1 100pF P CONTROL INPUTS 25 RD 26 WR 2 CS 3 4 5 6 7 8 9 10 11 12 13 14 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 28
Input Bandwidth
The ADC's input tracking circuitry has a 5MHz smallsignal bandwidth. When using the internal acquisition mode with an external clock frequency of 2MHz, a 100ksps throughput rate can be achieved. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
CLK DGND
MAX196 MAX198
27 VDD 23 REF 22 4.7F REFADJ 0.01F INT CH5 CH4 CH3 CH2 CH1 CH0 AGND 24 21 20 19 18 17 16 15
+5V 4.7F
0.01F OUTPUT STATUS
ANALOG INPUTS
P DATA BUS
Figure 4 shows the equivalent input circuit. The fullscale input voltage depends on the voltage at the reference (VREF). The MAX196 uses a scaling factor, which allows input voltage ranges of 10V, 5V, 0V to +10V, or 0V to +5V with a 4.096V voltage reference (Table 1). Program the desired range by setting the appropriate control bits (D3, D4) in the control byte (Tables 2 and 3). The MAX198 does not use a scaling factor, so its input voltage range directly corresponds with the reference voltage. It can be programmed for input voltages of VREF, VREF/2, 0V to VREF, or 0V to VREF/2 (Table 3). When an external reference is applied at REFADJ, the voltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V < VREF < 4.18V). The input channels are overvoltage protected to 16.5V. This protection is active even if the device is in power-down mode. Even with VDD = 0V, the input resistive network provides current-limiting that adequately protects the device.
Figure 3. Operational Diagram
Digital Interface
Input data (control byte) and output data are multiplexed on a three-state parallel interface. This parallel I/O can easily be interfaced with a P. CS, WR, and RD control the write and read operations. CS is the standard chip-select signal, which enables a P to address the MAX196/MAX198 as an I/O port. When high, it disables the WR and RD inputs and forces the interface into a high-Z state.
BIPOLAR S1 UNIPOLAR 5.12k R1 CH_ S2 ON R2 HOLD S3 TRACK TRACK OFF CHOLD
VOLTAGE REFERENCE
T/H OUT HOLD
Table 1. Full Scale and Zero Scale (MAX196 only)
RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE 0 to +5 0 0 -- -- -- -- VREF x 1.2207 VREF x 2.4414 0 to +10 5 10
S4
S1 = BIPOLAR/UNIPOLAR SWITCH R1 = 12.5k (MAX196) OR 5.12k (MAX198) S2 = INPUT MUX SWITCH R2 = 8.67k (MAX196) OR (MAX198) S3, S4 = T/H SWITCH
-VREF x 1.2207 VREF x 1.2207 -VREF x 2.4414 VREF x 2.4414
Figure 4. Equivalent Input Circuit
8 _______________________________________________________________________________________
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
Table 2. Control-Byte Format
D7 (MSB) PD1 D6 PD0 D5 ACQMOD D4 RNG D3 BIP D2 A2 D1 A1 D0 (LSB) A0
BIT 7, 6 5 4 3 2, 1, 0
NAME PD1, PD0 ACQMOD RNG BIP A2, A1, A0
DESCRIPTION These two bits select the clock and power-down modes (Table 4). 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition Selects the full-scale voltage magnitude at the input (Table 3). Selects unipolar or bipolar conversion mode (Table 3). These are address bits for the input mux to select the "on" channel (Table 5).
Table 3. Range and Polarity Selection
BIP 0 0 1 1 RNG 0 1 0 1 INPUT RANGE (V) (MAX196) 0 to 5 0 to 10 5 10 INPUT RANGE (V) (MAX198) 0 to VREF/2 0 to VREF VREF/2 VREF
Table 4. Clock and Power-Down Selection
PD1 PD0 0 0 1 1 0 1 0 1 DEVICE MODE Normal Operation / External Clock Mode Normal Operation / Internal Clock Mode Standby Power-Down (STBYPD); clock mode is unaffected Full Power-Down (FULLPD); clock mode is unaffected
Table 5. Channel Selection
A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 CH0 CH1 CH2 CH3 CH4 CH5

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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
Input Format The control byte is latched into the device, on pins D7-D0, during a write cycle. Table 2 shows the controlbyte format. Output Data Format The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When reading the output data, CS and RD must be low.
duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3s with f CLK = 2MHz) ends (see Figure 5).
How to Start a Conversion
Conversions are initiated with a write operation, which selects the mux channel and configures the MAX196/ MAX198 for either a unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external. The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle will abort the conversion and start a new acquisition interval.
External Acquisition Use the external acquisition timing mode for precise control of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR's rising edge (Figure 6). However, if the second control byte contains ACQMOD = 1, an indefinite acquisition interval is restarted. The address bits for the input mux must have the same values on the first and second write pulses. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode section).
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the device to flag the P when the conversion has ended and a valid result is available. INT goes low when conversion is complete and the output data is ready (Figures 5 and 6). It returns high on the first read cycle or if a new control byte is written. tCSRH
Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose
tCS
CS
tCSRS tACQI
tCSWS
WR
tWR tDS
tCSWH tDH
CONTROL BYTE
tCONV
D7-D0
ACQMOD ="0" INT
tINT1
RD
tD0
HIGH-Z DOUT DATA VALID
tTR
HIGH-Z
Figure 5. Conversion Timing Using Internal Acquisition Mode
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
tCS
CS
tCSRS
tCSRH
tCSWS
WR
tWR tDS
tACQI tCSHW tDH
tCONV
D7-D0
CONTROL BYTE ACQMOD = "1"
CONTROL BYTE ACQMOD = "0"
tINT1
INT
RD
tD0
DOUT DATA VALID
tTR
Figure 6. Conversion Timing Using External Acquisition Mode
Clock Modes
The MAX196/MAX198 operate with either an internal or an external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clock mode is selected, changing these bits to program power-down will not affect the clock mode. In each mode, internal or external acquisition can be used. At power-up, external clock mode is selected.
INTERNAL CLOCK PERIOD (ns)
2000
1500
Internal Clock Mode Select internal clock mode to free the P from the burden of running the SAR conversion clock. To select this mode, write the control byte with D7 = 0 and D6 = 1. A 100pF capacitor between the CLK pin and ground sets this frequency to 1.56MHz nominal. Figure 7 shows a linear relationship between the internal clock period and the value of the external capacitor used. External Clock Mode Select external clock mode by writing the control byte with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR timing relationships in internal and external acquisition modes, with an external clock. A 100kHz to 2.0MHz external clock with 45% to 55% duty cycle is required for proper operation. Operating at clock frequencies lower than 100kHz will cause a voltage droop across the hold capacitor, and subsequently degrade performance.
1000
500
0 0 50 100 150 200 250 300 350
CLOCK PIN CAPACITANCE (pF)
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS
CLK
tCWS
WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS HIGH
tCWH
CLK
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS LOW
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tDH
WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS HIGH ACQUISITION STARTS CLK ACQUISITION ENDS
tCWS
ACQMOD = "0"
CONVERSION STARTS
tDH
WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW
tCWH
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
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Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
__________Applications Information
Power-On Reset
At power-up, the internal power-on reset circuitry sets INT high and puts the device in normal operation/external clock mode. This state is selected to keep the internal clock from loading the external clock driver when the part is used in external clock mode.
MAX196 MAX198
AV = 1.638 REFADJ 10k 25 0.01F REF 26 4.096V 4.7F CREF
MAX196/MAX198
Internal or External Reference
The MAX196/MAX198 can operate with either an internal or external reference. An external reference can be connected to either the REF pin or the REFADJ pin (Figure 9). To use the REF input directly, disable the internal buffer by tying REFADJ to VDD. Using the REFADJ input eliminates the need to buffer the reference externally. When the reference is applied at REFADJ, bypass REFADJ with a 0.01F capacitor to AGND. The REFADJ internal buffer gain is trimmed to 1.6384 to provide 4.096V at the REF pin from a 2.5V reference.
2.5V
Figure 9a. Internal Reference
REF
26
4.096V 4.7F CREF
Internal Reference The internally trimmed 2.50V reference is gained through the REFADJ buffer to provide 4.096V at REF. Bypass the REF pin with a 4.7F capacitor to AGND and the REFADJ pin with a 0.01F capacitor to AGND. The internal reference voltage is adjustable to 1.5% (65 LSBs) with the reference-adjust circuit of Figure 1. External Reference At REF and REFADJ, the input impedance is a minimum of 10k for DC currents. During conversions, an external reference at REF must be able to deliver 400A DC load currents, and must have an output impedance of 10 or less. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor to AGND. With an external reference voltage of less than 4.096V at the REF pin or less than 2.5V at the REFADJ pin, the increase in the ratio of the RMS noise to the LSB value (FS / 4096) results in performance degradation (loss of effective bits).
MAX196 MAX198
AV = 1.638 REFADJ 10k 25
VDD
2.5V
Figure 9b. External Reference, Reference at REF
REF
26
4.096V 4.7F CREF
MAX196 MAX198
AV = 1.638 REFADJ 10k 25
Power-Down Mode
To save power, you can put the converter into lowcurrent shutdown mode between conversions. Two programmable power-down modes are available: STBYPD and FULLPD. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte. When power-down is asserted, it becomes effective only after the end of conversion. In all power-down modes, the interface remains active and conversion
2.5V 0.01F
2.5V
Figure 9c. The external reference overdrives the internal reference.
13
______________________________________________________________________________________
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
results may be read. Input overvoltage protection is active in all power-down modes. The device returns to normal operation on the first WR falling edge during write operation. than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50s for settling time. Throughput rates of 10ksps offer typical supply currents of 470A, using the recommended 33F capacitor value.
Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7F capacitor at the REF pin. This is a "DC" state that does not degrade after power-down of any duration. Therefore, you can use any sampling rate with this mode, without regard to start-up delays. However, in FULLPD mode, only the bandgap reference is active. Connect a 33F capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-down ends. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less
Auto-Shutdown Selecting STBYPD on every conversion automatically shuts the MAX196/MAX198 down after each conversion without requiring any start-up time on the next conversion.
Transfer Function
Output data coding for the MAX196/MAX198 is binary in unipolar mode with 1LSB = (FS / 4096) and twoscomplement binary in bipolar mode with 1LSB = [(2 x |FS|) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 10 and 11 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale (FS) values, refer to Table 1.
OUTPUT CODE 11... 111 11... 110 11... 101 FULL-SCALE TRANSITION 1 LSB =
FS 4096
OUTPUT CODE 1 LSB = 011... 111 011... 110
2FS 4096
000... 001 000... 000 111... 111
00... 011 00... 010 00... 001 00... 000 0 1 2 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
100... 010 100... 001 100... 000 -FS 0V INPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 10. Unipolar Transfer Function
Figure 11. Bipolar Transfer Function
14
______________________________________________________________________________________
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best system performance. For best performance, use a ground plane. To reduce crosstalk and noise injection, keep analog and digital signals separate. Digital ground lines can run between digital signal lines to minimize interference. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1F and 4.7F capacitors to AGND to minimize high- and low-frequency fluctuations. If the supply is excessively noisy, connect a 5 resistor between the supply and V DD , as shown in Figure 12.
SUPPLY +5V GND
MAX196/MAX198
4.7F R* = 5 0.1F ** VDD AGND DGND +5V DGND
MAX196 MAX198
DIGITAL CIRCUITRY
* OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
_________________________________________________________Functional Diagram
REF REFADJ 10k
CH5 CH4 CH3 CH2 CH1 CH0
SIGNAL CONDITIONING BLOCK & OVERVOLTAGE TOLERANT MUX
AV = 1.638
+2.5V REFERENCE
T/H CHARGE REDISTRIBUTION 12-BIT DAC 12 COMP
CLK
CLOCK
SUCCESSIVEAPPROXIMATION REGISTER CONTROL LOGIC & LATCHES 8 12 THREE-STATE, BIDIRECTIONAL I/O INTERFACE D0-D11 12-BIT DATA BUS
CS WR RD
INT
MAX196 MAX198
VDD AGND DGND
______________________________________________________________________________________
15
Multirange, Single +5V, 12-Bit DAS with 12-Bit Bus Interface MAX196/MAX198
_Ordering Information (continued)
PART MAX196BC/D MAX196AENI MAX196BENI MAX196AEWI MAX196BEWI MAX196AEAI MAX196BEAI MAX196AMYI MAX196BMYI MAX198ACNI MAX198BCNI MAX198ACWI MAX198BCWI MAX198ACAI MAX198BCAI MAX198BC/D MAX198AENI MAX198BENI MAX198AEWI MAX198BEWI MAX198AEAI MAX198BEAI MAX198AMYI MAX198BMYI TEMP. RANGE 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C PIN-PACKAGE Dice* 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Narrow Ceramic SB** 28 Narrow Ceramic SB** 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP Dice* 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Narrow Ceramic SB** 28 Narrow Ceramic SB**
0.144" (3.659mm) D2 CH5 D6 D5 D4 D3 D1 D0 AGND CH0 CH1 CH4 CH3 CH2 D9 D8 D7 INT REF 0.231" (5.870mm) REFADJ D10 RD
___________________Chip Topography
D11 CLK V DD CS DGND V CC WR
TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED TO GND
* Dice are specified at TA = +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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